On-line error detectable carry-free adder design

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2001, Pages 66-71

  Lala, P K ^a   Walker, A ^b  

^a University of Arkansas   (United States)

^b UNIVERSITY OF ARKANSAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; ERROR DETECTION; LOGIC CIRCUITS; RELIABILITY; VLSI CIRCUITS;

ADDER DESIGN; CARRY FREE ADDERS; ERROR CHECKING CAPABILITY; SIGNED BINARY DIGITS;

ADDERS;

EID: 0035193790     PISSN: 10636722     EISSN: None     Source Type: Journal    
DOI: 10.1109/DFTVS.2001.966753     Document Type: Article

References (7)

1. An SFS Berger check prediction ALU and its application to self-checking processor design
2. A tool for generation of self-checking data paths
3. A self-checking ALU design with efficient codes
4. Efficient implementation self-checking adders and ALUs
5. Signed-digit number representations for fast parallel arithmetic
6. A high-speed multiplier using a redundant binary adder tree