Analytical solutions for interconnect stress in board level drop impact

IEEE Transactions on Advanced Packaging

Volumn 30, Issue 4, 2007, Pages 654-664

  Wong, E Hua ^a,b   Mai, Yiu Wing ^b   Seah, Simon K W ^a   Lim, Kian Meng ^c   Lim, Thiam Beng ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b UNIVERSITY OF SYDNEY   (Australia)

^c NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Analytical solutions; Drop impact; Electronic packaging; Electronics packaging; Integrated circuit manufacture; Mechanical shocks; Stress analysis

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; PRINTED CIRCUIT BOARDS; SHOCK PROBLEMS; STRAIN; STRAIN MEASUREMENT; STRESS ANALYSIS;

ANALYTICAL SOLUTIONS; BOARD LEVEL DROP IMPACT; INTERCONNECT STRESS; MECHANICAL SHOCKS;

ELECTRONICS PACKAGING;

EID: 36348989735     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2007.898599     Document Type: Article

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