New insights into board level drop impact

Microelectronics Reliability

Volumn 46, Issue 5-6, 2006, Pages 930-938

  Wong, E H ^a,b   Mai, Y W ^a  

^a UNIVERSITY OF SYDNEY   (Australia)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

BENDING (DEFORMATION); FLEXIBLE COUPLINGS; INTERCONNECTION NETWORKS; METHOD OF MOMENTS; STRESSES;

BENDING MOMENT; BOARD LEVEL DROP IMPACT; INTERCONNECTION STRESS; LOAD BEARING AREA;

PRINTED CIRCUIT BOARDS;

EID: 33645132650     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2005.07.114     Document Type: Conference Paper

References (16)

1. JEDEC Standard JESD22-B111. Board level drop test method of components for handheld electronic products.
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3. Lim CT et al. Drop impact survey of portable electronic products. In: Proc 53rd ECTC, 2003.
4. Wong EH et al. Tackling board level drop impact reliability of electronic interconnections. Interpack 2003.
5. Wong EH et al. Drop impact test-mechanics and physics of failure. In: Proc 4th EPTC, 2002. p. 327-33.
6. Wong EH et al. Fundamentals of drop impact. Presented in JEDEC working group meeting, December 2003.
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16. Wong EH et al. Board level drop impact-fundamental and parametric analysis. ASME, JEP, in press.