EUV mask pattern inspection using current DUV reticle inspection tool

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6607, Issue PART 1, 2007, Pages

  Abe, Tsukasa ^a   Fujii, Akiko ^a   Sasaki, Shiho ^a   Mohri, Hiroshi ^a   Imai, Hidemichi ^a   Takaya, Hironobu ^a   Sato, Yasushi ^a   Hayashi, Naoya ^a   Maenaka, Yumiko ^b  

^a DAI NIPPON PRINTING CO LTD   (Japan)

^b KLA TENCOR CORPORATION   (United States)

Author keywords

45 nm node; 65nm node; Defect; EUV; EUVL; Inspection; Mask

Indexed keywords

CIRCUIT SIMULATION; DEFECTS; EXTREME ULTRAVIOLET LITHOGRAPHY; INSPECTION; NANOTECHNOLOGY; PRINTED CIRCUITS;

BUFFER ETCH PATTERN; MASK PATTERNS; SENSITIVITY DIFFERENCE; WAFER PRINT SIMULATION;

MASKS;

EID: 36248986113     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.728935     Document Type: Conference Paper

References (3)

1. Do Young Kim et al., "EUV mask Pattern inspection for Memory Mask Fabrication in 45nm node and below" Proceedings of SPIE, Vol. 6349, 6349L, 2006.
2. G. Zhang et al, "EUV Mask Process Development and Integration Proceeding of SIPE Vol. 6283, 62830G, 2006
3. T.Abe et al. "Process development for EUV mask production" Proceedings of SPIE, Vol. 6349, 63493G, 2006.