Commercial EUV mask blank readiness for 32 nm HP manufacturing

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6607, Issue PART 1, 2007, Pages

  Seidel, Phil ^a  

^a SEMATECH   (United States)

Author keywords

Blank; Coefficient of thermal expansion (CTE); Cost of ownership; Defects; EUV; Flatness; Mask; Reflectivity; Substrate; Wavelength

Indexed keywords

EXTREME ULTRAVIOLET LITHOGRAPHY; INTEGRATED CIRCUIT MANUFACTURE; PRINTED CIRCUITS; THERMAL EXPANSION; WAVELENGTH;

COST OF OWNERSHIP; MASK BLANK MATERIALS;

MASKS;

EID: 36248969187     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.728931     Document Type: Conference Paper

References (7)

1. International Technology Roadmap for Semiconductors, 2006 (ITRS-06); http://www.itrs.net/Links/2006Update/FinalToPost/08_Lithography2006Update.pdf (as updated)
2. SEMI P37-1102 Specification for Extreme Ultraviolet Lithography Mask Substrates; Semiconductor Equipment and Materials International); San Jose CA; Nov. 2002.
3. SEMI P38-1103 Specification for Absorbing Film Stacks and Multilayers on Extreme Ultraviolet Lithography Mask Blanks; Semiconductor Equipment and Materials International); San Jose CA; Nov. 2003.
4. P. Seidel, "EUV mask blank readiness for 45- nm HP 2009 manufacturing," Proc. SPIE Vol. 5751, 178 (2005)
5. Sommargren et al; "Characterizing the flatness, wedge and homogeneity of EUVL mask substrates," 1st EUVL Symposium, Dallas TX, Oct. 2002.
6. T. Sugiyama et al, "Development of EUVL mask blanks in AGC"; Proc. SPIE Vol. 6349, 63492J (Oct. 20, 2006)
7. rd Inter. Conf European Society for Precision Engineering and Nanotechnology: 2 (2002), 691