Hardware architecture for a general regression neural network coprocessor

Neurocomputing

Volumn 71, Issue 1-3, 2007, Pages 78-87

  Lázaro, Jesús ^a   Arias, Jagoba ^a   Astarloa, Armando ^a   Bidarte, Unai ^a   Zuloaga, Aitzol ^a  

^a UNIVERSITY OF THE BASQUE COUNTRY UPV EHU   (Spain)

Author keywords

FPGA; GRNN; Matlab; Neural networks; SoPC

Indexed keywords

COMPUTER SOFTWARE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MATLAB; SOFTWARE ARCHITECTURE;

GENERAL REGRESSION NEURAL NETWORK; SYSTEM ON PROGRAMMABLE CHIP;

NEURAL NETWORKS;

ACCURACY; ARCHITECTURE; ARTICLE; ARTIFICIAL NEURAL NETWORK; COMPUTER; COMPUTER PROGRAM; COMPUTER SIMULATION; CONTROLLED STUDY; DEVICE; INTERMETHOD COMPARISON; MATHEMATICAL COMPUTING; PRIORITY JOURNAL; TASK PERFORMANCE; TRAINING; VELOCITY;

EID: 35648998908     PISSN: 09252312     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.neucom.2007.01.012     Document Type: Article

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