300-mm low-k wafer dicing saw development

IEEE Transactions on Electronics Packaging Manufacturing

Volumn 30, Issue 4, 2007, Pages 313-319

  Wang, ZhiJie ^a   Wang, J H ^a   Lee, Stephen ^a   Yao, SuYing ^b   Han, Richard ^a   Su, Yeqing Q ^a  

^a Freescale Inc   (China)

^b TIANJIN UNIVERSITY   (China)

Author keywords

Delamination; Interlayer dielectric; Reticle; Step cut

Indexed keywords

CUTTING; DELAMINATION; DIELECTRIC MATERIALS;

INTERLAYER DIELECTRIC; RETICLE; STEP CUT; WAFER DICING;

SILICON WAFERS;

EID: 35348882140     PISSN: 1521334X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEPM.2007.906488     Document Type: Article

References (4)

1. "International Technology Roadmap for Semiconductors," SIA, 2005 [Online]. Available: http://www.itrs.net
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3. T. Scherban, B. Sun, J. Blaine, C. Block, B. Jin, and E. Andideh, "Interfacial adhesion of copper-low k interconnects," in Proc. IEEE Int. Interconnect Technol. Conf., 2001, pp. 257-259.
4. S. Allada, ""Low k adhesion issues in Cu/low k integration," in Proc. IEEE Int. Interconnect Technol. Conf., 1999, pp. 161-163.