High-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches

Proceedings - IEEE INFOCOM

Volumn 1, Issue , 1997, Pages 20-28

  Duan, Haoran ^a   Lockwood, J W ^a   Kang, S M ^a   Will, J D ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER STORAGE; DATA COMMUNICATION EQUIPMENT; DATA COMMUNICATION SYSTEMS; DATA PROCESSING; INTELLIGENT NETWORKS; LOGIC GATES; MULTICHIP MODULES; SWITCHING SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HEAD OF LINE (HOL) BLOCKING; MATRIX UNIT CELL SCHEDULER (MUCS); THREE DIMENSIONAL QUEUE (3DQ);

ASYNCHRONOUS TRANSFER MODE;

EID: 0031373074     PISSN: 0743166X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (30)