FPGA architecture design and toolset for logic implementation

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2799, Issue , 2003, Pages 607-616

  Tatas, K ^a   Siozios, K ^a   Vasiliadis, N ^b   Soudris, D J ^a   Nikolaidis, S ^b   Siskos, S ^b   Thanailakis, A ^a  

^a DEMOCRITUS UNIVERSITY OF THRACE   (Greece)

^b ARISTOTLE UNIVERSITY OF THESSALONIKI   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; ENERGY UTILIZATION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); NETWORK ARCHITECTURE;

CONFIGURABLE LOGIC BLOCKS; CRITICAL STEPS; DESIGN SUPPORT TOOLS; DETAILED DESIGN; FPGA ARCHITECTURES; FPGA PROGRAMMING; INTERCONNECT NETWORKS; TOOL DEVELOPMENT;

INTEGRATED CIRCUIT DESIGN;

EID: 35248852818     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-39762-5_67     Document Type: Article

References (14)

1. Katherine Compton and Scott Hauck: Reconfigurable Computing: A Survey of Systems and Software. ACM Computing Surveys, Vol. 34, No. 2 (2002) 171-210
2. http://direct.xilinx.com/bvdocs/publications/ds003.pdf
3. http://www.altera.com/products/software/sfw-index.jsp
4. Vaughn Betz and Jonathan Rose: VPR: A New Packing, Placement and Routing Tool for FPGA Research, in Proc. of FPL '97, London, UK (1997) 213-222.
5. UCLA
6. http://www.mentor.com/leonardospectrum/datasheet.pdf
7. http://www.eecg.toronto.edu/~jayar/software/edif2blif/edif2blif.html
8. M. Sentovich, K. J. Singh, L. Lavagno, et al.: SIS: A System for Sequential Circuit Synthesis. UCB/ERL M92/41 (1992)
9. V. Betz and J. Rose: Cluster-Based Logic Blocks for FPGAs: Area-Efficiency vs. Input Sharing and Size. IEEE Custom Integrated Circuits Conference, Santa Clara, CA (1997) 551-554
10. Elias Ahmed, Jonathan Rose: The effect of LUT and cluster size on deep-submicron FPGA performance and density. FPGA 2000 (2000) 3-12
11. Kara KW Poon: Power Estimation for Field-Programmable Gate Arrays. Master of Applied Science Dissertation, University of British Columbia (2002)
12. V. Betz and J. Rose: Effect of the Prefabricated Routing Track Distribution on FPGA Area-Efficiency. IEEE Transactions on VLSI Systems (1998) 445-456
13. V. Betz and J. Rose: FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA (1999) 59-68
14. MCNC benchmarks