Offset assignment showdown: Evaluation of DSP address code optimization algorithms

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2622, Issue , 2003, Pages 290-302

  Leupers, Rainer ^a  

^a RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION PROGRAMS; BENCHMARKING; C (PROGRAMMING LANGUAGE); COMBINATORIAL OPTIMIZATION; PROGRAM COMPILERS;

ADDRESS CODE; ASSIGNMENT PROBLEMS; BENCHMARK SUITES; C COMPILERS; EMPIRICAL EVALUATIONS; REAL-LIFE APPLICATIONS; SIMPLE OFFSET ASSIGNMENTS; SPECIAL CLASS;

OPTIMIZATION;

EID: 35248844096     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-36579-6_21     Document Type: Review

References (24)

1. S. Liao: Code Generation and Optimization for Embedded Digital Signal Processors, Ph.D. thesis, Depf. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1996
2. S. Udayanarayanan, C. Chakrabarti: Address Code Generation for Digital Signal Processors, 38th Design Automation Conference (DAC), 2001
3. S. Liao, S. Devadas, K. Keutzer, S. Tjiang, A. Wang: Storage Assignment to Decrease Code Size, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1995
4. R. Leupers, P. Marwedel: Algorithms for Address Assignment in DSP Code Generation, Int. Conference on Computer-Aided Design (ICCAD), 1996
5. D.H. Bartley: Optimizing Stack Frame Accesses for Processors with Restricted Addressing Modes, Software - Practice and Experience, vol. 22(2), 1992
6. Target Compiler Technologies: http://www.retarget.com
7. M.R. Gary, D.S. Johnson: Computers and Intractability - A Guide to the Theory of NP-Completeness, Freemann, 1979
8. B. Wess: Minimization of Data Address Computation Overhead in DSPs, 3rd Int. Workshop on Code Generation for Embedded Processors (SCOPES), 1998
9. A. Rao, S. Pande: Storage Assignment using Expression Tree Transformations to Generate Compact and Efficient DSP Code, ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1999
10. V. Zivojnovic, J.M. Velarde, C. Schläger, H. Meyr: DSPStone - A DSP-oriented Benchmarking Methodology, Int. Conf. on Signal Processing Applications and Technology (ICSPAT), 1994
11. R. Leupers, F. David: A Uniform Optimization Technique for Offset Assignment Problems, 11th Int. System Synthesis Symposium (ISSS), 1998
12. S. Atri, J. Ramanujam, M. Kandemir: Improving Offset Assignment for Embedded Processors, Languages and Compilers for High-Performance Computing, S. Midkiff et al. (eds.), Lecture Notes in Computer Science, Springer, 2001
13. N. Sugino, H. Miyazaki, S. Iimuro, A. Nishihara: Improved Code Optimization Method Utilizing Memory Addressing Operations and its Application to DSP Compilers, Int. Symp. on Circuits and Systems (ISCAS), 1996
14. B. Wess, M. Gotschlich: Constructing Memory Layouts for Address Generation Units Supporting Offset 2 Access, Proc. ICASSP, 1997
15. N. Kogure, N. Sugino, A. Nishihara: Memory Address Allocation Method for a DSP with ± 2 Update Operations in Indirect Addressing, European Conference on Circuit Theory and Design (ECCTD), 1997
16. A. Sudarsanam, S. Liao, S. Devadas: Analysis and Evaluation of Address Arithmetic Capabilities in Custom DSP Architectures, Design Automation Conference (DAC), 1997
17. B. Wess, M. Gotschlich: Optimal DSP Memory Layout Generation as a Quadratic Assignment Problem, Int. Symp. on Circuits and Systems (ISCAS), 1997
18. E. Eckstein, A. Krall: Minimizing Cost of Local Variables Access for DSP Processors, ACM Workshop on Languages, Compilers, and Tools for Embedded Systems (LCTES), 1999
19. C. Liem, P. Paulin, A. Jerraya: Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures, 33rd Design Automation Conference (DAC), 1996
20. C. Gebotys: DSP Address Optimization Using a Minimum Cost Circulation Technique, Int. Conference on Computer-Aided Design (ICCAD), 1997
21. R. Leupers, A. Basu, P. Marwedel: Optimized Array Index Computation in DSP Programs, Asia South Pacific Design Automation Conference (ASP-DAC), 1998
22. W.-K. Cheng, Y.-L. Lin: Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture, 11th Int. System Synthesis Symposium (ISSS), 1998
23. G. Ottoni, S. Rigo, G. Araujo, S. Rajagopalan, S. Malik: Optimal Live Range Merge for Address Register Allocation in Embedded Programs, 10th International Conference on Compiler Construction (CC), 2001
24. LANCE C Compiler: http://LS12-www.cs.uni-dortmund.de/lance