Optimal SRAF placement for process window enhancement in 65nm/45nm technology

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 6520, Issue PART 2, 2007, Pages

  Sarma, Chandra ^a   Herold, Klaus ^a   Noelscher, Christoph ^b   Schroeder, Paul ^a  

^a INFINEON TECHNOLOGIES   (United States)

^b QIMONDA DRESDEN GMBH AND CO OHG   (Germany)

Author keywords

Assist features; Asymmetrical SRAF; Forbidden pitch; Gate; OPC; Process window; SRAF

Indexed keywords

MASKS;

ASSIST FEATURES; ASYMMETRICAL SRAF; FORBIDDEN PITCH; PROCESS WINDOW; SPACE LIMITATIONS;

FEATURE EXTRACTION;

EID: 35148880296     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.711480     Document Type: Conference Paper

References (4)

1. C. Sarma et al., "Finding the right way: DFM vs. area efficiency for 65nm gate layer lithography", Optical Microlithography XIX, Proc. Of SPIE Vol6154 61541L-1 ,2006
2. Lars W Liebmann et al, "Optimizing Style Options for Sub-Resolution Assist Features" SPIE Proc vol4346, pp141-152, 2001
3. Chi-Yuan Hung et al., "A Novel Approach for Full Chip SRAF Printability Check", Optical Microlithography XIX, Proc. Of SPIE Vol6154 615438 ,2006
4. Paul Schroeder et al, "ACLV performance dry vs. immersion on 45nm ground rules", ML6520-179, Submitted to SPIE 2007