Folded fat H-Tree: An interconnection topology for dynamically reconfigurable processor array

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3207, Issue , 2004, Pages 301-311

  Yamada, Yutaka ^a   Amano, Hideharu ^a   Koibuchi, Michihiro ^a   Jouraku, Akiya ^a   Anjo, Kenichiro ^a   Nishimura, Katsunobu ^b  

^a KEIO UNIVERSITY   (Japan)

^b CHIBA UNIVERSITY OF COMMERCE   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT INTERCONNECTS; TOPOLOGY; UBIQUITOUS COMPUTING;

DYNAMICALLY RECONFIGURABLE PROCESSORS; EVALUATION RESULTS; FAT H TREES; INTERCONNECTION TOPOLOGIES; ON-CHIP IMPLEMENTATIONS; ON-CHIP NETWORKS; RECONFIGURABLE PROCESSORS; STREAM PROCESSING;

FORESTRY;

EID: 35048885612     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30121-9_29     Document Type: Article

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