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Volumn 2964, Issue , 2004, Pages 25-38

Design of AES based on dual cipher and composite field

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN; HARDWARE; STANDARDS;

EID: 35048848990     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-24660-2_3     Document Type: Article
Times cited : (10)

References (16)
  • 1
    • 0003508558 scopus 로고    scopus 로고
    • FIPS Publication 197, Nov.
    • National Institute of Standards and Technology (NIST). Advanced Encryption Standard (AES). FIPS Publication 197, Nov. 2001. Available at http://csrc.nist.gov/encryption/aes/index.html.
    • (2001) Advanced Encryption Standard (AES)
  • 2
    • 84958748914 scopus 로고    scopus 로고
    • In How Many Ways Can You Write Rijndael
    • E. Barkan, E. Biham. In How Many Ways Can You Write Rijndael. Asiacrypt 2002, pp.160-175, 2002.
    • (2002) Asiacrypt 2002 , pp. 160-175
    • Barkan, E.1    Biham, E.2
  • 3
    • 84944877872 scopus 로고    scopus 로고
    • Efficient Rijndael Encryption Implementation with Composite Field Arithmetic
    • CHES 2001
    • A. Rudra, P. Dubey, C. Jutla, V. Kumar, J. Rao, P. Rohatgi. Efficient Rijndael Encryption Implementation with Composite Field Arithmetic. CHES 2001, LNCS 2162, pp.171-184 2001.
    • (2001) LNCS , vol.2162 , pp. 171-184
    • Rudra, A.1    Dubey, P.2    Jutla, C.3    Kumar, V.4    Rao, J.5    Rohatgi, P.6
  • 4
    • 84944896938 scopus 로고    scopus 로고
    • An ASIC Implementation of the AES Sboxes
    • CT-RSA 2002
    • J. Wolkerstorfer, E. Oswald, M, Lamberger. An ASIC Implementation of the AES Sboxes. CT-RSA 2002, LNCS 2271, pp.67-78, 2002.
    • (2002) LNCS , vol.2271 , pp. 67-78
    • Wolkerstorfer, J.1    Oswald, E.2    Lamberger, M.3
  • 6
    • 35248861095 scopus 로고    scopus 로고
    • Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm
    • CHES 2001
    • H. Kua, I. Verbauwhede. Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm. CHES 2001, LNCS 2162, pp.51-64, 2001.
    • (2001) LNCS , vol.2162 , pp. 51-64
    • Kua, H.1    Verbauwhede, I.2
  • 7
    • 84946832086 scopus 로고    scopus 로고
    • A Compact Rijndael Hardware Architecture with S-Box Optimization
    • Asiacrypt 2001
    • A. Satoh, S. Morioka, K. Takano, and S. Munetoh. A Compact Rijndael Hardware Architecture with S-Box Optimization. Asiacrypt 2001, LNCS 2248, pp.239-254, 2001.
    • (2001) LNCS , vol.2248 , pp. 239-254
    • Satoh, A.1    Morioka, S.2    Takano, K.3    Munetoh, S.4
  • 8
    • 84944878412 scopus 로고    scopus 로고
    • High performance single-chip FPGA Rijndael algorithm implementations
    • CHES 2001
    • M. McLoone et al. High performance single-chip FPGA Rijndael algorithm implementations. CHES 2001, LNCS 2162, pp.65-76, 2001.
    • (2001) LNCS , vol.2162 , pp. 65-76
    • McLoone, M.1
  • 9
    • 35248894915 scopus 로고    scopus 로고
    • An Optimized S-Box Circuit Architecture for Low Power AES Design
    • CHES 2002
    • S. Morioka and A. Satoh. An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES 2002, LNCS 2523, pp.172-186, 2003.
    • (2003) LNCS , vol.2523 , pp. 172-186
    • Morioka, S.1    Satoh, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.