System redundancy; A means of improving process variation yield degradation in memory arrays

2006 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2006 - Proceedings of Technical Papers

Volumn , Issue , 2007, Pages 139-142

  Eltawil, Ahmed M ^a   Kurdahi, Fadi J ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; PARAMETER ESTIMATION; SPECIFICATION LANGUAGES; STORAGE ALLOCATION (COMPUTER); WIRELESS TELECOMMUNICATION SYSTEMS;

MEMORY ARRAYS; MEMORY YIELD; NANO-SEALE DEVICES; SYSTEM DESIGN PARAMETER; SYSTEM REDUNDANCY;

SYSTEMS ENGINEERING;

EID: 34748916996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2006.258144     Document Type: Conference Paper

References (7)

1. X. Wang, M. Ottavi, F. Meyer, F. Lombardi," On the yield of compiler-based eSRAMs,'' in Proceedings of International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 11-19, 2004.
2. A. Agarwal, B.C. Paul, H. Mahmoodi, A. Datta, K. Roy, "A process-tolerant Cadhe architecture for improved yield in nanoscale technologies," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 13, Issue 1, pp. 27-38, Jan. 2005.
3. C. Berrou, A. Glavieux, P. Thitimajshima, »Near Shanon Limit Error Correcting Coding and Decoding : Turbo Codes ", in proc. IEEE International Conference on Communications, Geneva, Switzerland, Vol. 2/3, pp. 1064-1071, May 1993.
4. Ahmed M. Eltawil et al. "Dual Antenna UMTS Mobile Station Transceiver ASIC for ,2 Mbps Data," in Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), p. 146-47, vol. 46,Feb. 2003.
5. W.E. Ryan," A Turbo Code Tutorial," New Mexico State University [Online], available: http://www.ece.arizona.edu /-ryan/turbo2c.pdf.
6. 3GPP TS25.212 V3.5.0 Multiplexing and channel coding (FDD)
7. Y. Hamamura et al.,"Repair yield simulation with iterative critical area analysis for different types of failure," in Proceedings of IEEE International Symposium oh Defect and Fault Tolerance in VLSI Systems, pp. 305-313, Nov. 2002.