Post-route LUT output polarity selection for timing optimization

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2007, Pages 89-96

  Zhu, Kai ^a  

^a Actel Corp   (United States)

Author keywords

FPGA lookup table; Optimization; Polarity; Timing

Indexed keywords

ALGORITHMS; MULTIPLEXING; NETWORK ARCHITECTURE; OPTIMIZATION; TIME DELAY;

FPGA LOOKUP TABLE; ROUTING MULTIPLEXERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34748846322     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1216919.1216932     Document Type: Conference Paper

References (8)

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