Analysis of data dependence of leakage current in CMOS cryptographic hardware

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2007, Pages 78-83

  Giorgetti, Jacopo ^a   Scotti, Giuseppe ^a   Simonetti, Andrea ^a   Trifiletti, Alessandro ^a  

^a SAPIENZA UNIVERSITY OF ROME   (Italy)

Author keywords

Cryptographic hardware; Leakage power consumption; Side channel analysis

Indexed keywords

COMPUTER HARDWARE; CRYPTOGRAPHY; ELECTRIC POWER UTILIZATION; LEAKAGE CURRENTS; MEASUREMENT THEORY; SECURITY OF DATA;

CRYPTOGRAPHIC HARDWARE; LEAKAGE POWER CONSUMPTION; SIDE CHANNEL ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 34748821079     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1228784.1228808     Document Type: Conference Paper

References (12)

1. P. Kocher, J. Jaffe and B. Jun, "Differential Power Analysis," Advances in Cryptology, Santa Barbara, Aug. 1999, Lecture Notes in Computer Science, vol. 1666, 1999, pp. 388-397.
2. M. Bucci, M. Guglielmo, R. Luzzi, and A. Trifiletti, "A power consumption randomization countermeasure for DPA resistant cryptographic processors." in PATMOS, 2004, pp. 481-490.
3. A. Shamir, "Protecting smart cards from passive power analysis with detached power supplies," in CHES '00: Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems. London, UK: Springer-Verlag, 2000, pp. 71-77.
4. S. Narendra, S. Borkar, V. De, D. Antoniadis, A. Chandrakasan, "Scaling of stack effect and its application for leakage reduction" International Symposium on Low Power Electronics and Design 2001, pp. 195-200.
5. S. Bobba, and I. N. Hajj "Maximum leakage power estimation for CMOS circuits" IEEE Proc. on Low Power Design, March 1999 pp. 116-124.
6. Antoni Ferrè, and Joan Figueras "On estimating leakage power consumption for submicron CMOS digital circuits" IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation, Louvain La Neuve, Belgium, September 1997.
7. Afshin Abdollahi, Farzan Fallah, and Massoud Pedram "Leakage current reduction in CMOS VLSI circuits by input vector controll", IEEE Trans. on VLSI Systems, vol. 12, no. 2, 2004, pp. 140-154.
8. Zhanping Chen, Liqiong Wei, Mark Johnson, and Kaushik Roy "Estimation of standby leakage power in CMOS circuits considering accurate modelling of transistor stacks" International Symposium on Low Power Electronics and Design, Aug 1998 pp. 239-24
9. Yannis Tsividis "Operation and Modeling of the Transistor MOS" second edition, Oxford University Press, 2003.
10. Geoff Merrett and Bashir M. Al-Hashimi "Leakage power analysis and comparison of deep submicron logic gates" IEEE International Workshop on Power And Timing Modeling, Optimization and Simulation, pp. 198-207, Santorini, Greece, 2004.
11. R. Anderson, E. Biham, and L. Kundsen, A proposal for the Advanced Encryption Standard, AES proposal, 1998, available at http://www.cl.cam.ac.uk/ ftp/users/rja14/serpent.pdf.
12. M. Aigner, S. Mangard, F. Menichelli, R. Menicocci, M. Olivieri, T. Popp, G. Scotti, A. Trifiletti, "A.Side channel analysis resistant design flow"; IEEE International Symposium on Circuits and Systems, 21-24 May 2006.