Low-power CMOS comparator with embedded amplification for ultra-high-speed ADCs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3602-3605

  Oliveira, J P ^a   Goes, J ^a   Esperanca B ^a   Paulino, N ^a   Fernandes, J ^b  

^a UNINOVA   (Portugal)

^b INESC ID   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; SWITCHING NETWORKS;

PREAMPLIFICATION; SWITCHED CAPACITOR NETWORKS;

COMPARATOR CIRCUITS;

EID: 34548858984     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378532     Document Type: Conference Paper

References (13)

1. T. N. Andersen, et. al., "A Cost Efficient High-Speed 12-bit Pipeline ADC in 0.18-um Digital CMOS", IEEE JSSC, no. 7, pp.1506-1513, 2005.
2. Frank Goodenough, "Analog Technology of All Varieties Dominate ISSCC", Electronic Design, No. 19, pp. 96-111, 1996.
3. B. Vaz, N. Paulino, J. Goes, R. Costa, R. Tavares and A. Steiger-Garção, "Design of Low-Voltage CMOS Pipelined ADC's using 1 pico-Joule of Energy per Conversion", Proc. IEEE International Symposium on Circuits and Systems, Arizona, USA, May 2002.
4. K. Kharkevich, "Nonlinear and Parametric Phenomena in Radio Engineering", K. Pullen, Ed. New York: Rider 1962
5. S. Ranganathan, Y. Tsividis, "A MOS capacitor-based discrete-time parametric amplifier with 1.2 V output swing and 3uW power dissipation", IEEE ISSCC. Dig. Tech. Papers, pp. 406-407, Feb. 2003.
6. S. Ranganathan, Y. Tsividis, "Discrete-Time parametric amplification, based on a three-terminal MOS varactor: analisys and experimental results", IEEE, J. Solid-State Circuits, no. 12, pp. 2087-2093, Dec. 2003.
7. P. Figueiredo, J. Vital, "The MOS capacitor amplifier", IEEE, Tran.Circ. and Systems-II: Express brief, no. 3, pp. 111-115, Mar. 2004.
8. J. Wu, B. Wooley "A 100-MHz pipelined CMOS comparator", IEEE, J. Solid-State Circuits, vol. 23, no. 6, pp. 1379-1385, Dec. 1988.
9. K. Kotani, et. al., "CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power, high-accuracy comparators", IEEE, Symp. on VLSI Circuits, Dig Tech. Papers, pp 21-22, 1997;
10. T. Shih et al. "A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection", IEEE, J. Solid-State Circuits, vol. 32, no. 2, pp. 250-253, Dec. 2003.
11. B. Razavi, B. Wooley "Design techniques for high-speed, high-resolution comparators", IEEE, JSSC, no. 12, pp. 1916-1926, Dec. 1992.
12. J. Fernandes, M. Silva, "Asymmetric Latches and Nonideal Performance of Parallel ADCs", MELCON'94, pp. 629-632, 1994.
13. P. Cusimato et al., "Analysis of the behavior of a dynamic latch comparator", IEEE, Trans. on Circuits and Systems-I: Theory and Applications, vol. 45, no. 3, pp. 294-298, Mar. 1998.