A 1.2-to-8V charge-pump with improved power efficiency for non-volatile memories

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 522-524

  Richelli, A ^a   Mensi, L ^a   Colalongo, L ^a   Rolandi, P L ^b   Kovacs Vajna Zs M ^a  

^a UNIVERSITY OF BRESCIA   (Italy)

^b STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; ENERGY EFFICIENCY; POWER SUPPLY CIRCUITS;

CHARGE-PUMP ARCHITECTURE; FAVRAT CELLS; NON-VOLATILE MEMORIES;

DATA STORAGE EQUIPMENT;

EID: 34548852230     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373524     Document Type: Conference Paper

References (6)

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2. J. Shin et al., "A New Charge Pump Without Degradation in Threshold Voltage due to Body Effect," IEEE J. Solid-State Circuits, pp. 1227-1230, Aug., 2000.
3. J. T. Wu et al., "MOS Charge Pumps for Low-Voltage Operation," IEEE J. Solid-State Circuits, pp. 592-597, Apr., 1998.
4. R. Pelliconi et al., "Power Efficient Charge Pump in Deep Submicron Standard CMOS Technology," IEEE J. Solid-State Circuits, pp. 1088-1071, June. 2003.
5. L. Mensi et al., "A New Integrated Charge Pump Architecture using Dynamic Biasing of Pass-Transistors," Proc. ESSCIRC, pp. 86-88, 2005.
6. G. Palumbo, D. Pappalardo and M. Gaibotti, "Charge-Pump Circuits: Power-Consumption Optimization," IEEE T. CAS I, pp. 1535-1542, Nov., 2002.