DRAM scaling-down to 0.1 μm generation using bitline spacerless storage node SAC and RIR capacitor with TiN contact plug

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 127-128

  Jin, B J ^a   Kim, Y P ^a   Nam, B Y ^a   Kim, H J ^a   Park, Y W ^a   Moon, J T ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; DIFFUSION; ELECTRIC CONTACTS; ELECTRIC RESISTANCE; EPITAXIAL GROWTH; LEAKAGE CURRENTS; SEMICONDUCTOR JUNCTIONS; TITANIUM NITRIDE; TRANSISTORS;

SELF-ALIGNED CONTACTS (SAC);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034798940     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)