High-speed/low-power mixed full adder chains: Analysis and comparison versus technology

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2998-3001

  Alioto, Massimo ^a   Palumbo, Gaetano ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC NETWORK TOPOLOGY; HIGH SPEED NETWORKS; INTEGRATED CIRCUIT LAYOUT; MIXER CIRCUITS;

DOWN-SCALED TECHNOLOGIES; POWER-DELAY DESIGNS; SINGLE-TOPOLOGY CIRCUITS; TECHNOLOGY NODES;

ADDERS;

EID: 34548841125     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.377977     Document Type: Conference Paper

References (9)

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