A fractional-N PLL for digital clock generation with an FIR-embedded frequency divider

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 3051-3054

  Chi, Baoyong ^a   Yu, Xueyi ^a   Rhee, Woogeun ^a   Wang, Zhihua ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

EMBEDDED SYSTEMS; FIR FILTERS; FREQUENCY DIVIDING CIRCUITS; NOISE ABATEMENT; SEQUENTIAL CIRCUITS; VECTOR QUANTIZATION;

DIGITAL CLOCK GENERATION; MULTIMODULUS DIVIDERSS; OVER SAMPLING RATIO (OSR); QUANTIZATION NOISE REDUCTION;

PHASE LOCKED LOOPS;

EID: 34548841123     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2007.378052     Document Type: Conference Paper

References (8)

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