FPGA implementation of base-N logarithm

Proceedings - 2007 3rd Southern Conference on Programmable Logic, SPL'07

Volumn , Issue , 2007, Pages 27-32

  Tropea, Salvador E ^a  

^a INSTITUTO NACIONAL DE TECNOLOGÍA INDUSTRIAL   (Argentina)

Author keywords

Area optimized; FPGA; Logarithm; Multiplicative normalization

Indexed keywords

ALGORITHMS; FREQUENCY MULTIPLYING CIRCUITS; RANDOM ACCESS STORAGE;

AREA OPTIMIZED; LOGARITHM; MULTIPLICATIVE NORMALIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34548836557     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SPL.2007.371719     Document Type: Conference Paper

References (9)

1. M. Haselman, M. Beauchamp, A. Wood, et al, "A Comparison of Floating Point and Logarithmic Number Systems for FPGAs," Proc. of the 13th Annual IEEE Symp. on Field-Prog Custom Comp. (FCCM'05) 0-7695-2445, Jan. 2005.
2. Y. Wan and C. L. Wey, "Efficient algorithms for binary logarithmic conversion and addition," IEE Proc.-Comp. Digit. Tech., vol. 146, no. 3, May. 1999.
3. T. C. Chen, "Automatic computation of exponential, logarithms rations and square roots," IBM J. Res. Develop., pp. 380-388, Jul. 1972.
4. H.-Y. Lo and Y. Aoki, "Generation of a precise binary logarithm with difference grouping programmable logic array," IEEE Trans. Comput., vol. C-34, pp. 681-691, Aug. 1985.
5. S.-Y. Shi, "Shortcut to logarithms combine table lookup and computation," Comput. Design., pp. 186-189, May. 1976.
6. nd edition," ISBN 1-56881-160-8, pp. 225-232.
7. D. K. Kostopoulos, "An algorithm for the computation of binary logarithms," IEEE Trans. on Comp., vol. 40, no. 11, 0018-9340/91, Nov. 1991.
8. B. Parhami, "Computer Arithmetic Algorithms and Hardware Designs," ISBN 0-19-512583-5, pp 378-381.
9. M. Pascale, "Microcontrollers & CORDIC methods,", Dr. Dobb's Journal, http://www.ddj.com/184404244, Jul. 2001.