A VLSI architecture for a high-speed computation of the 1-D discrete wavelet transform

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1461-1464

  Zhang, Chengjun ^a   Wang, Chunyan ^a   Ahmad, M Omair ^a  

^a Civil and Environmental Engineering   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DATA FLOW; DATA PATHS; HIGH-SPEED COMPUTATION; IN-BETWEEN; MULTIPLE INPUTS; PROCESSING ELEMENTS; PROCESSING TIME; PROPOSED ARCHITECTURES; VERILOG SIMULATION; VLSI ARCHITECTURES;

CELLULAR RADIO SYSTEMS; DISCRETE WAVELET TRANSFORMS;

PIPELINE PROCESSING SYSTEMS;

EID: 34548834944     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464874     Document Type: Conference Paper

References (8)

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