Discrete-time modeling of clock jitter in continuous-time ΔΣ modulators

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 497-500

  Chopp, Philip M ^a   Hamoui, Anas A ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

JITTER; MATHEMATICAL MODELS; MODULATORS; POWER SPECTRUM; TRANSFER FUNCTIONS;

CLOCK JITTER; IMPULSE-INVARIANT TRANSFORM; NON-RETURN-TO-ZERO (NRZ); RETURN-TO-ZERO (RZ);

DISCRETE TIME CONTROL SYSTEMS;

EID: 34548822479     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. J. A. Cherry and W. M. Snelgrove, Continuous-time delta-sigma modulators for high-speed A/D conversion: theory, practice and fundamental performance limits. Boston: Kluwer, 2000.
2. L. Hernandez et al., "Modelling and optimization of low pass continuous-time sigma-delta modulators for clock jitter noise reduction," in Proc. IEEE Int. Symp. Circuits Syst., pp. 1072 -1075, May 2004.
3. P. Benabes and R. Kielbasa, "Fast clock-jitter simulation in continuoustime delta-sigma modulators," in Proc. IEEE Instr. and Meas. Conf., pp. 1587-1590, May 2001.
4. A. A. Hamoui and K. W. Martin, "High-order multibit modulators and pseudo data-weighted-averaging in low-oversampling ΔΣ ADCs for broad-band applications," IEEE Trans. Circuits Syst. I, vol. 51, no. 1, pp. 72-85, Jan. 2004.