A novel RF-WAT test structure for advanced process monitoring in SOC applications

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2007, Pages 243-247

  Chen, David C ^a   Lee, Ryan ^a   Liu, Y C ^a   Tang, Mao Chyuan ^a   Chiang, Gavin ^a   Kuo, Annie ^a   Yeh, C S ^a   Chien, S C ^a   Sun, S W ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; FUNCTION EVALUATION; STATISTICAL METHODS; WSI CIRCUITS;

FUNCTION VERIFICATION; GSSG STRUCTURE;

PROCESS MONITORING;

EID: 34548821887     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICMTS.2007.374492     Document Type: Conference Paper

References (3)

1. I. Ahsan, et al, "RTA-Driven Intra-die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology," Symp. VLSI Tech, Dig., 2006, pp. 66-67
2. Liang-Teck Pang and Boøivoje Nikolic, "Impact of Layout on 90nm CMOS Process Parameter Fluctuations," Symp. VLSI Tech, Dig., 2006, pp. 48-49
3. Jurriaan Schmitz, Florence N. Cubaynes, Ramon J. Havens, Randy de Kort, Andries J. Schölten, and Luuk F. Tiemeijer, "Test Structure Design Considerations for RF-CV Measurements on Leaky Dielectrics," IEEE Trans. Semiconductor Manufacturing, vol. 17, no. 2, May 2004, pp150-154.