Hardware architectures for the Tate pairing over GF(2m)

Computers and Electrical Engineering

Volumn 33, Issue 5-6, 2007, Pages 392-406

  Keller, Maurice ^a   Ronan, Robert ^a   Marnane, William ^a   Murphy, Colin ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

BKLS GHS algorithm; Cryptography; Hardware architecture; Tate pairing

Indexed keywords

ALGORITHMS; COMPUTATIONAL METHODS; CRYPTOGRAPHY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); OPTIMIZATION; PARALLEL PROCESSING SYSTEMS;

DESIGN PARAMETERS; TATE PAIRING;

COMPUTER ARCHITECTURE;

EID: 34548498830     PISSN: 00457906     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.compeleceng.2007.05.002     Document Type: Article

References (19)

1. Dutta R, Barua R, Sarkar P. Pairing-based cryptographic protocols: a survey, 2004. Cryptology ePrint Archive, .
2. Sklavos N., and Koufopavlou O. Mobile communications world: security implementation aspects - a state of the art. CSJM J 11 2 (2003) 168-187
3. Miller VS. Short programs for functions on curves. Unpublished manuscript, 1986, .
4. Barreto PSLM, Kim HY, Lynn B, Scott M. Efficient algorithms for pairing-based cryptosystems. In: Proceedings of the 22nd annual international cryptology conference (CRYPTO '02), LNCS 2442, 2002, p. 354-68.
5. Galbraith SD, Harrison K, Soldera D. Implementing the Tate pairing. In: Proceedings of the fifth algorithmic number theory symposium (ANTS-V), LNCS 2369, 2002, p. 324-37.
6. p - x + d. In: Proceedings of the 9th international conference on the theory and application of cryptology and information security (ASIACRYPT '03), LNCS 2894, 2003, p. 111-23.
7. Barreto PSLM, Galbraith S, O'hEigeartaigh C, Scott M. Efficient pairing computation on supersingular Abelian varieties. 2004, Cryptology ePrint Archive, .
8. 4m) inverter and its application in a Tate pairing processor. In: Proceedings of the 3rd international conference on reconfigurable computing and FGPAs 2006 (ReConFig'06), IEEE; 2006. p. 158-69.
9. Kerins T., Marnane W.P., Popovici E.M., and Barreto P.L.S.M. Hardware accelerators for pairing based ryptosystems. IEE Proc Inform Security 152 1 (2005) 47-56
10. m). In: Proceedings of design automation and test in Europe 2006 (DATE '06), 2006. p. 7-11.
11. Ronan R, O'hEigeartaigh C, Murphy C, Scott M, Kerins T, Marnane WP. An embedded processor for a pairing-based cryptosystem. In: Proceedings of the third international conference on information technology: new generations, 2006 (ITNG 2006), IEEE, 2006. p. 192-7.
12. Kerins T, Marnane W, Popovici E, Barreto P. Efficient hardware for the Tate pairing calculation in characteristic 3. In: Proceedings of cryptographic hardware and embedded systems (CHES 2005), LNCS 3659, 2005. p. 412-26.
13. Grabher P, Page D. Hardware acceleration of the Tate pairing in characteristic 3. In: Proceedings of cryptographic hardware and embedded systems (CHES 2005), LNCS 3659, 2005. p. 398-411.
14. Bertoni G, Breveglieri L, Fragneto P, Pelosi G. Parallel hardware architectures for the cryptographic Tate pairing. In: Proceedings of the third international conference on information technology: new generations (ITNG'06), IEEE; 2006. p. 186-91.
15. m) Tate pairing architecture. In: Proceedings of the international workshop on applied reconfigurable computing (ARC2006), LNCS 3985, 2006. p. 358-69.
16. 4m) multiplier for use in pairing based cryptosystems. In: Proceedings of the international conference on field programmable logic and applications. IEEE, 2005. p. 594-97.
17. Song L., and Parhi K. Low energy digit-serial/parallel finite field multipliers. Kulwer J VLSI Signal Process Syst 19 2 (1998) 149-166
18. Shantz SC. From Euclid's GCD to Montgomery multiplication to the great divide. TR-2001-95, Technical Report, Sun Microsystems; 2001.
19. Celoxica RC2000. .