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Volumn 3985 LNCS, Issue , 2006, Pages 358-369
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FPGA implementation of a GF(2m) tate pairing architecture
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTATIONAL METHODS;
MATHEMATICAL OPERATORS;
PROGRAM PROCESSORS;
SECURITY SYSTEMS;
SCALAR MULTIPLICATION;
SECURITY LEVELS;
FIELD PROGRAMMABLE GATE ARRAYS;
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EID: 33749017046
PISSN: 03029743
EISSN: 16113349
Source Type: Book Series
DOI: 10.1007/11802839_44 Document Type: Conference Paper |
Times cited : (11)
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References (15)
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