Bitwise scheduling to balance the computational cost of behavioral specifications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 1, 2006, Pages 31-46

  Molina, M C ^a   Ruiz Sautua, R ^a   Mendias, J M ^a   Hermida, R ^a  

^a UNIVERSIDAD COMPLUTENSE DE MADRID   (Spain)

Author keywords

Allocation algorithms; Behavioral specifications; Bit level algorithm; Bitwise scheduling; Circuit synthesis; Clock cycle length; Data formats; Data widths; Design automation; Hardware resources; Nonconsecutive cycles; Operation fragmentation

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; COMPUTER HARDWARE; DATA STRUCTURES; INTEGRATED CIRCUITS; RESOURCE ALLOCATION;

ALLOCATION ALGORITHMS; BEHAVIORAL SPECIFICATIONS; BIT-LEVEL ALGORITHMS; BITWISE SCHEDULING; CLOCK-CYCLE LENGTH; DATA FORMATS; DATA WIDTHS; HARDWARE RESOURCES; NONCONSECUTIVE CYCLES; OPERATION FRAGMENTATION;

SCHEDULING;

EID: 31344438946     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.852663     Document Type: Article

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