Scalable reconfigurable channel decoder architecture for future wireless handsets

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 1563-1568

  Krishnaiah, Gummidipudi ^a   Engin, Nur ^b   Sawitzki, Sergei ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

BLUETOOTH; COMPUTATIONAL METHODS; CONSUMER ELECTRONICS; SIGNAL RECEIVERS; TELEPHONE SETS; WIRELESS LOCAL AREA NETWORKS (WLAN);

CHANNEL DECODER ARCHITECTURE; COMMUNICATION STANDARDS; DIGITAL RECEIVERS;

WIRELESS TELECOMMUNICATION SYSTEMS;

EID: 34548324115     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364524     Document Type: Conference Paper

References (13)

1. Bickerstaff, M. A., Garrett, D., Prokop, T., Thomas, C., Widdup, B., Zhou, G., Davis, L. M.: A Unified Turbo/Viterbi Channel Decoder for 3GPP Mobile Wireless in 0.18-mm CMOS, IEEE Journal of Solid-State Circuits, November 2002, pp. 1555-1564
2. Thomas, C., Bickerstaff, M. A., Davis, L. M., Prokop, T., Widdup, B., Zhou, G., Garrett, D., Nichol, C.: Integrated Circuits for Channel Coding in 3G Cellular Mobile Wireless Systems, IEEE Communications Magazine, August 2003, pp. 150-159.
3. Kreiselmaier G., Vogt T., Wehn N.: Combined Turbo and Convolutions Decoder Architecture for UMTS Wireless Applications, Proceedings of DATE, February 2004, pp 192-197.
4. Cavallaro, J. R., Vaya, M.: VITURBO: A Reconfigurable Architecture for Viterbi and Turbo Decoding, Proceedings of ICASSP '03, April 2003, pp. 497-500
5. Robertson P., Villebrun, E. and Hoeher, P.: A Comparison of Optimal and Sub-optimal MAP decoding algorithms operating in Log domain, Proc. IEEE ICC, Seattle, WA, USA, Jun 18-22, 1995, pp. 1009-13.
6. Chatzigeorgiou, I. A., Rodrigues, M. R. D., Wassell, I. J., and Carrasco, R.: A Comparison of Convolutions and Turbo Coding Schemes for Broadband FWA Systems, 12th International Conference on Telecommunications, Cape Town, South Africa, May 2005.
7. Joeressen O. J., and Meyr, H.: 40 Mb/sSoft-Output Viterbi Decoder, IEEE Journal of Solid State Circuits, vol.30 July 1995, pp. 812-818.
8. Engin, N.: Turbo decoder architecture with scalable parallelism, in Proceedings of IEEE Workshop on Signal Processing Systems, 2004, pp. 298-303
9. Berns, F., Kreiselmaier, G., Wehn, N.: Channel Decoder Architecture for 3G Mobile Wireless Terminals, Proceedings of DATE Conference, February 2004, pp. 192-197
10. Yoon S., Bar-Ness Y.: A parallel MAP algorithm for low latency turbo decoding, Communication Letters IEEE, vol.6 Jul 2002, pp.288-290.
11. Bekooij, M., Dielissen, J., Harmsze, F., Sawitzki, S., van der Werf, A., van Meerbergen ,J.: Power-Efficient Application-Specific VLIW Processor for Turbo Decoding, in Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC'2001), February 2001
12. Harmsze, F., Dielissen, J.: Implementation of a Turbo Decoding for 3G - a turbo decoding processor, Nat.Lab. Technical Report 7178, Philips Research, 2001
13. Bi, L., Pu, T., Sawitzki, S.: Architecture Study of 480 Mbps Viterbi Decoder for OFDM-UWB: Towards implementation in silicon, Nat.Lab. Technical Note PR-TN 2004/00779, Philips Research, 2004