A turbo decoder architecture with scalable parallelism

IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation

Volumn , Issue , 2004, Pages 298-303

  Engin, Nur ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CODE DIVISION MULTIPLE ACCESS; COMPUTER ARCHITECTURE; COMPUTER PROGRAMMING; DATA REDUCTION; DECODING; ENERGY UTILIZATION; ERROR ANALYSIS; STORAGE ALLOCATION (COMPUTER); TABLE LOOKUP; VECTORS;

DATA MEMORY; DECODER ARCHITECTURE; POWER CONSUMPTION; TURBO DECODERS;

TURBO CODES;

EID: 17044393082     PISSN: 15206130     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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