Power-efficient application-specific VLIW processor for turbo decoding

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 180-181

  Bekooij, M ^a   Dielissen, J ^a   Harmsze, F ^a   Sawitzki, S ^a   Huisken, J ^a   Van der Werf, A ^a   Van Meerbergen, J ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; DECODING; ERROR CORRECTION; PROGRAM COMPILERS; TURBO CODES;

TURBO DECODING;

PROGRAM PROCESSORS;

EID: 0035054821     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Near shannon limit error-correcting coding and decoding: Turbo codes
2. Phideo: High-level synthesis for high throughput applications
3. Scheduling coarse grain operations for VLIW processors