The use of condition maps in the design and testing of power electronic circuits and devices

IEEE Transactions on Industry Applications

Volumn 43, Issue 4, 2007, Pages 902-910

  Bryant, Angus T ^a   Parker Allotey, Nii Adotei ^b   Palmer, Patrick R ^b  

^a UNIVERSITY OF WARWICK   (United Kingdom)

^b UNIVERSITY OF CAMBRIDGE   (United Kingdom)

Author keywords

Conditions; Device testing; Load cycles; Optimization; Power semiconductor devices

Indexed keywords

ELECTRIC INVERTERS; NETWORKS (CIRCUITS); OPTIMIZATION; POWER ELECTRONICS; SEMICONDUCTOR DEVICES;

LOAD CYCLES; POWER ELECTRONIC CIRCUITS; POWER SEMICONDUCTOR DEVICES;

SEMICONDUCTOR DEVICE TESTING;

EID: 34547915611     PISSN: 00939994     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIA.2007.900470     Document Type: Article

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