High speed word-parallel bit-serial normal basis finite field multiplier and its FPGA implementation

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn 2005, Issue , 2005, Pages 1338-1341

  Namin, Ashkan Hosseinzadeh ^a   Huapeng, Wu ^a   Ahmadi, Majid ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL ANALYSIS; FINITE FIELDS; HIGH SPEED WORD;

COMPUTER SIMULATION; FREQUENCY MULTIPLYING CIRCUITS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 33847658333     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

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2. Lidl, R. and Niederreiter, H. "Introduction to Finite Fields and Their Applications ", 2nd Edition, Cambridge, England. Cambridge University Press, 1997.
3. R. C. Mullin, I. M. Onyszchuk, S. A. Vanstone, and R. M. Wilson "Optimal normal bases in GF(pn)", Discrete Applied Mathematics, Volume 22, Issue 2 (February 1989), pp. 149 - 161.
4. Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhong Gao, "Finite Field Multiplier Using Redundant Representation. ", IEEE Trans. Computers 51(11): 1306-1316 (2002)
5. Shuhong Gao and Scott A. Vanstone, "On orders of optimal normal basis generators," Mathematics of Computation vol.64 no.211, (jul.,1995), pp 1227--1233.
6. J.L.Messay and J.K.Omura, "Computational Method and Aparatus for Finite Field Arithmetic," US Patent No. 4,587,627 to OMNET Assoc., Sunnyvale CA, Washington, D.C.: Patent and Trademark Office, 1986.