Low-power motion-estimation architecture based on a novel early-jump-out technique

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 5, Issue , 2001, Pages 187-190

  Zhang, Wujian ^a   Zhou, Runde ^a   Kondo, Toshio ^b  

^a TSINGHUA UNIVERSITY   (China)

^b MIE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM LEVEL; ARCHITECTURAL ENHANCEMENT; ARCHITECTURE-BASED; BLOCK MATCHING; BLOCK-MATCHING MOTION ESTIMATION; LOW POWER; SIMILAR IMAGE;

VLSI CIRCUITS;

ALGORITHMS; COMPUTER SIMULATION; IMAGE QUALITY; MATHEMATICAL MODELS; MOTION ESTIMATION; SYSTOLIC ARRAYS;

EARLY-JUMP-OUT-DECISION (EJOD) UNITS;

EID: 0035023218     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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