Design of a 270 MHz/340 mW processing element for high performance motion estimation systems application

Microelectronics Journal

Volumn 33, Issue 12, 2002, Pages 1123-1134

  Lopez J Fco ^a   Cortes P ^a   Lopez S ^a   Sarmiento, R ^a  

^a UNIVERSITY OF LAS PALMAS DE GRAN CANARIA   (Spain)

Author keywords

Block matching; Gallium arsenide; Motion estimation; MPEG; VLSI

Indexed keywords

ALGORITHMS; BANDWIDTH; COMMUNICATION CHANNELS (INFORMATION THEORY); SEMICONDUCTING GALLIUM ARSENIDE;

VIDEO PROCESSING;

MOTION ESTIMATION;

EID: 0036895056     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2692(02)00118-0     Document Type: Conference Paper

References (14)

1. Jain J.R., Jain A.K. Displacement measurement and its application in interframe image coding. IEEE Trans. Commun. COM-29:1981;1799-1808.
2. Ishiguro T. Motion-compensated interframe coding for video conferencing. Proc. Nat. Telecommun. Conf., New Orleans, LA. November:1981.
3. Kappagantula S., Rao K.R. Motion compensated predictive interframe coding. IEEE Trans. Commun. COM-33:1985.
4. Srinivasan R., Rao K.R. Predictive coding based on efficient motion estimation. IEEE Trans. Commun. COM-33:1985.
5. Liu B., Zaccarin A. New fast algorithms for the estimation of block motion vectors. IEEE Trans. Circuits Syst. Video Technol. 3:1993.
6. Komarek T., Pirsch P. Array architectures for block matching algorithms. IEEE Trans. Circuits Syst. 36:(10):1989;1301-1308.
7. Yang K.M., Sun M.T., Wu L. A family of VLSI designs for the motion compensation block-matching algorithm. IEEE Trans. Circuits Syst. 36:(10):1989.
8. De Vos L., Stegherr M. Parameterizable VLSI architectures for the full search block matching algorithm. IEEE Trans. Circuits Syst. 36:(10):1989;1309-1316.
9. Hsieh C.H., Lin T.P. VLSI architecture for block-matching motion estimation algorithm. IEEE Trans. Circuits Syst. Video Technol. 2:(2):1992;169-175.
10. Jehng Y.S., Chen L.G. An efficient and simple VLSI tree architecture for motion estimation algorithms. IEEE Trans. Signal Process. 41:(2):1993.
11. Yeo H., Hu Y.H. A novel modular systolic array architecture for full-search block matching motion estimation. IEEE Trans. Circuits Syst. Video Technol. 5:1995;407-416.
12. Vitesse Semiconductor Corporation, Vitesse H-GaAs III Foundry Design Manual, 1993.
13. Sarmiento R., Carballo P.P., Núñez A. High speed primitives of hardware accelerators for DSP in GaAs technology. IEE Proc. G. 139:(2):1992;205-216.
14. Eshraghian K., Sarmiento R., Carballo P.P., Núñez A. Speed-area-oower optimization for DCFL and SDCFL class of logic using ring notation, Microprocessing and Microprogramming. vol. 32:1991;North-Holland, Amsterdam. pp. 75-82.