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Volumn , Issue , 2004, Pages 161-168

On the placement and granularity of FPGA configurations

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION MODELS; MEMORY ARCHITECTURES; RUNTIME MANAGEMENT SYSTEMS; VIRTUAL ADDRESS SPACE;

EID: 20844446787     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (18)

References (23)
  • 2
    • 84860952377 scopus 로고    scopus 로고
    • Open cores Inc. www.opencores.org.
  • 3
    • 79951736247 scopus 로고    scopus 로고
    • Xilinx, Inc.
    • JBits SDK. Xilinx, Inc., 2000.
    • (2000) JBits SDK
  • 8
    • 21144446219 scopus 로고    scopus 로고
    • Exploiting redundancy to speedup reconfiguration of an FPGA
    • I. Kennedy. Exploiting redundancy to speedup reconfiguration of an FPGA. Field Programmable Logic, pages 262-271, 2003.
    • (2003) Field Programmable Logic , pp. 262-271
    • Kennedy, I.1
  • 9
    • 4143138809 scopus 로고    scopus 로고
    • Platform-independent methodology for partial reconfiguration
    • D. Kock and J. Teich. Platform-independent methodology for partial reconfiguration. Conference on Computing Frontiers, pages 398-403, 2004.
    • (2004) Conference on Computing Frontiers , pp. 398-403
    • Kock, D.1    Teich, J.2
  • 15
    • 84949795228 scopus 로고    scopus 로고
    • Automated extraction of run-time parametrisable cores from programmable device configurations
    • P. Roxby and S. Guccione. Automated extraction of run-time parametrisable cores from programmable device configurations. IEEE Workshop on Field Programmable Custom Computing Machines, pages 153-161, 2000.
    • (2000) IEEE Workshop on Field Programmable Custom Computing Machines , pp. 153-161
    • Roxby, P.1    Guccione, S.2
  • 17
    • 33845535510 scopus 로고    scopus 로고
    • Optimal reconfiguration sequence management
    • S. G. M. Sarrafzadeh. Optimal reconfiguration sequence management. Design Automation Conference, pages 359-365, 2003.
    • (2003) Design Automation Conference , pp. 359-365
    • Sarrafzadeh, S.G.M.1
  • 19
    • 84962194782 scopus 로고    scopus 로고
    • Dynamic hardware plugins (DHP): Exploiting reconfigurable hardware for high-performance programmable routers
    • D. Taylor, J. Turner, and J. Lockwood. Dynamic hardware plugins (DHP): Exploiting reconfigurable hardware for high-performance programmable routers. IEEE Open Architectures and Network Programming, pages 25-34, 2001.
    • (2001) IEEE Open Architectures and Network Programming , pp. 25-34
    • Taylor, D.1    Turner, J.2    Lockwood, J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.