Design of FPGA interconnect for multilevel metalization

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 154-163

  Rubin, Raphael ^a   DeHon, André ^a  

^a CALIFORNIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

FPGA; Hierarchical; Interconnect; Mesh of trees; Multi level metalization

Indexed keywords

COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUIT LAYOUT; INTERCONNECTION NETWORKS; VLSI CIRCUITS;

MESH-OF-TREES; MULTILEVEL METALIZATION;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038011090     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611839.611841     Document Type: Conference Paper

References (19)

1. A. A. Agarwal and D. Lewis. Routing Architectures for Hierarchical Field Programmable Gate Arrays. In Proceedings 1994 IEEE International Conference on Computer Design, pages 475-478. IEEE, October 1994.
2. V. Betz and J. Rose. FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. In Proceedings of the 1999 International Symposium on Field Programmable Gate Arrays (FPGA '99), pages 59-68, February 1999.
3. V. Betz and J. Rose. FPGA Place-and-Route Challenge. 1999.
4. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massaschusetts, 02061 USA, 1999.
5. M. Bohr. Interconnect Scaling - The Real Limiter to High Performance ULSI. In International Electron Devices Meeting 1995 Technical Digest, pages 241-244. Electron Devices Society of IEEE, December 1995.
6. S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic. Field-Programmable Gate Arrays. Kluwer Academic Publishers, 101 Philip Drive, Assinippi Park, Norwell, Massachusetts, 02061 USA, 1992.
7. W. S. Carter, K. Doung, R. H. Freeman, H.-C. Hsieh, J. Y. Ja, J. E. Mahoney, L. T. Ngo, and S. L. Sze. A User Programmable Reconfigurable Logic Array. In IEEE 1986 Custom Integrated Circuits Conference, IEEE, May 1986.
8. Y.-W. Chang, D. F. Wong, and C. K. Wong. Universal Switch-Module Design for Symmetric-Array-Based FPGAs. In Proceedings of the 1996 International Symposium on Field-Programmable Gate Arrays, ACM/SIGDA, February 1996.
9. A. DeHon. Compact, Multilayer Layout for Butterfly Fat-Tree. In Proceedings of the Twelfth ACM Symposium on Parallel Algorithms and Architectures (SPAA'2000), pages 206-215. ACM. July 2000.
10. A. DeHon. Rent's Rule Based Switching Requirements. In Proceedings of the System-Level Interconnect Prediction Workshop (SLIP'2001), pages 197-204. ACM, March 2001.
11. W. E. Donath, Placement and Average Interconnection Lengths of Computer Logic. IEEE Transactions on Circuits and Systems, 26 (4): 272-277, April 1979.
12. A. E. Gannal. Two-Dimensional Stochastic Model for Interconnections in Master Slice Integrated Circuits. IEEE Transactions on Circuits and Systems, 28(2): 127-138, February 1981.
13. B. S. Landman and R. L. Russo. On Pin Versus Block Relationship for Partitions of Logic Circuits. IEEE Transactions on Computers, 20:1469-1479, 1971.
14. F. T. Leighton. New lower bound techniques for VLSI. In Twenthy-Second Annual Symposium on the Foundations of Computer Science. IEEE, 1981.
15. F. T. Leighton. Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes. Morgan Kaufmann Publishers, Inc., 1992.
16. L. McMurchie and C. Ebling. PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 111-117. ACM, February 1995.
17. G. A. Sai-Halasz. Performance Trends in High-End Processors. Proceedings of the IEEE, 83(1) 20-36, January 1995.
18. W. Tsu, K. Macy, A. Joshi, R. Huang, N. Walker, T. Tung, O. Rowhani, V. George, J. Wawrzynek, and A. DeHon. HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125-134, February 1999.
19. Y.-L. Wu, S. Tsukiyama, and M. Marek-Sadowska. Graph Based Analysis of 2-D FPGA Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(1): 33-44, January 1996.