SCOPUS 정보 검색 플랫폼

Volumn , Issue , 2006, Pages 333-334

Design of a reconfigurable processor for NIST prime field ECC

Author keywords

[No Author keywords available]

Indexed keywords

CURVE FITTING; DIGITAL ARITHMETIC; LOGIC DESIGN; PUBLIC KEY CRYPTOGRAPHY;

ELLIPTIC CURVE CRYPTOGRAPHIC (ECC) OPERATIONS; RECONFIGURABLE PROCESSORS; SUBTRACTION;

PROGRAM PROCESSORS;

EID: 34547402134 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/FCCM.2006.36 Document Type: Conference Paper

Times cited : (2)

References (9)

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- Hankerson, D.¹ Menezes, A.² Vanstone, S.³

2
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- National Institute of Standards and Technology, FIPS Publication 186
- National Institute of Standards and Technology, Digital Signature Standard, FIPS Publication 186, 2000.
- (2000) Digital Signature Standard

3
- 0141747355
- A scalable GF(p) elliptic curve processor architecture for programmable hardware, Workshop on Cryptographic Hardware and Embedded Systems
- G. Orlando and C. Paar, "A scalable GF(p) elliptic curve processor architecture for programmable hardware," Workshop on Cryptographic Hardware and Embedded Systems, Springer LNCS 2162, pp. 356-371, 2001.
- (2001) Springer LNCS , vol.2162 , pp. 356-371
- Orlando, G.¹ Paar, C.²

4
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- Hardware implementation of an elliptic curve processor over GF(p)
- S. Ors et al, "Hardware implementation of an elliptic curve processor over GF(p)," IEEE Conf. on Application-Specific Systems, Architectures and Processors, pp. 433-443, 2003.
- (2003) IEEE Conf. on Application-Specific Systems, Architectures and Processors , pp. 433-443
- Ors, S.¹

5
- 2642517965
- An FPGA implementation of a GF(p) ALU for encryption processors
- A. Daly et al, "An FPGA implementation of a GF(p) ALU for encryption processors," Elsevier Microprocessors and Microsystems 28, pp. 252-260, 2004.
- (2004) Elsevier Microprocessors and Microsystems , vol.28 , pp. 252-260
- Daly, A.¹

6
- 29844444327
- A timing-and-area tradeoff GF(p) elliptic curve processor architecture for FPGA
- W. Shuhua and Z. Yuefei, "A timing-and-area tradeoff GF(p) elliptic curve processor architecture for FPGA," IEEE Conf. on Communications, Circuits and Systems, pp. 1308-1312, 2005.
- (2005) IEEE Conf. on Communications, Circuits and Systems , pp. 1308-1312
- Shuhua, W.¹ Yuefei, Z.²

7
- 27644456617
- High-level synthesis for large bit-width multipliers on FPGAs: A case study
- G. Quan et al, "High-level synthesis for large bit-width multipliers on FPGAs: a case study," ACM/IEEE Conf. on Hardware/Software Codesign and System Synthesis, pp. 213-218, 2005.
- (2005) ACM/IEEE Conf. on Hardware/Software Codesign and System Synthesis , pp. 213-218
- Quan, G.¹

8
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- m), Workshop on Cryptographic Hardware and Embedded Systems
- m)," Workshop on Cryptographic Hardware and Embedded Systems, Springer LNCS 2523, pp. 500-514, 2002.
- (2002) Springer LNCS , vol.2523 , pp. 500-514
- Wolkerstorfer, J.¹

9
- 0038300434
- A scalable dual-field elliptic curve cryptographic processor
- A. Satoh and K. Takano, "A scalable dual-field elliptic curve cryptographic processor," IEEE Trans. Computers, vol. 52, no. 4, pp. 449-460, 2003.
- (2003) IEEE Trans. Computers , vol.52 , Issue.4 , pp. 449-460
- Satoh, A.¹ Takano, K.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.