A new current-mode incremental signaling scheme with applications to Gb/s parallel links

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 4026-4029

  Tao, Wang ^a   Fei, Yuan ^a  

^a RYERSON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; ELECTRIC IMPEDANCE; SPURIOUS SIGNAL NOISE; TELECOMMUNICATION LINKS;

CHANNEL TERMINATION; HIGH FREQUENCY NOISE; NOISE INJECTION; SIGNAL INTEGRITY;

SIGNAL PROCESSING;

EID: 34547381724     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. A. Carusone, K. Farzan, and D. Johns, "Differential, Signaling with a Reduced Number of Signal paths," IEEE Trans. on CAS. II, Vol. 48, No. 3, pp. 294-300, March 2001.
2. LVDS Owner's Manual, National Semiconductor, 3rd ed. 2004.
3. J. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE JSSC, Vol.31, No. 11, pp. 1723-1732, Nov. 1996.
4. T. Gabara and S. Knauer, "Digitally adjustable resistors in CMOS for high-performance applications," IEEE JSSC, vol. 27, No. 8, pp. 1176-1185, August 1992.
5. S. Mohan, M. Hershenson, S. Boyd, and T. Lee, "Bandwidth Extension in CMOS with Optimized on-chip Inductors," IEEE JSSC, vol. 35, No. 3, pp. 346-355, 2000.
6. D.J. Foley and M.P.Flynn, "A Low-Power 8-PAM serial transceiver in 0.5μm digital CMOS," IEEE JSSC, vol. 37, No. 3, pp. 310-316, March 2002.
7. S. Sidiropoulos and M, Horowitz, "A 700-Mb/s/pin CMOS Signaling Interface Using Current Integrating Receivers," IEEE JSSC. vol. 32, No. 5, pp. 681-690, May 1997.