Decoders for low-density parity-check convolutional codes with large memory

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 5103-5106

  Bates, Stephen ^a   Gunthorpe, Logan ^a   Pusane, Ali Emre ^b   Chen, Zhengang ^a   Zigangirovt, Kamil ^b   Costello Jr , Daniel J ^b  

^a UNIVERSITY OF ALBERTA   (Canada)

^b University of Notre Dame   (United States)

Author keywords

Convolutional codes; Data communication; Error correction coding; High speed integrated circuits

Indexed keywords

BLOCK CODES; DECODING; ERROR CORRECTION; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PACKET NETWORKS; WIRELESS SENSOR NETWORKS;

ARBITRARY LENGTHS; DECODERS; ERROR CONTROL; ERROR CORRECTION CODING; HIGH-SPEED INTEGRATED CIRCUITS; PACKET SWITCHING NETWORKS;

CONVOLUTIONAL CODES;

EID: 34547371457     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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8. A. Sridharan and D. Costello Jr., "A new construction method for low density parity check convolutional codes," in Proceedings of The IEEE Information Theory Workshop, October 2002, p. 212.
9. R. Swamy, S. Bates, and T. L. Brandon, "Architectures for ASIC implementations of low-density parity-check convolutional encoders and decoders," in Proceedings of the IEEE Symposium on Circuits and Systems (ISCAS), Kobe, Japan, 2005.
10. S. Howard, C. Schlegel, and V. Gaudet, "A degree-matched check node approximation for LDPC decoding," in Proceedings of the IEEE Intl. Symposium on Information Theory, ISIT, Adelaide, Australia, September 2005.