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Volumn , Issue , 2007, Pages 606-611

An integer linear programming based routing algorithm for flip-chip design

Author keywords

Detailed routing; Global routing; Physical design

Indexed keywords

INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; PROBLEM SOLVING; ROUTING ALGORITHMS; VLSI CIRCUITS;

EID: 34547354319     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375235     Document Type: Conference Paper
Times cited : (54)

References (7)
  • 1
    • 0038037500 scopus 로고    scopus 로고
    • Wirelength reduction by using diagonal wire
    • G. Chiang, Q. Su, and C.-S. Chiang, "Wirelength reduction by using diagonal wire," Proc. of GLSVLSI, pp. 104-107, 2003.
    • (2003) Proc. of GLSVLSI , pp. 104-107
    • Chiang, G.1    Su, Q.2    Chiang, C.-S.3
  • 4
    • 34547358184 scopus 로고    scopus 로고
    • http://lpsolve.sourceforge.net/5.5/.
  • 5
    • 29144534070 scopus 로고    scopus 로고
    • A global routing method for 2-layer ball grid array packages
    • Y. Kubo and A. Takahashi, "A global routing method for 2-layer ball grid array packages," Proc. of ISPD, pp. 36-43, 2006.
    • (2006) Proc. of ISPD , pp. 36-43
    • Kubo, Y.1    Takahashi, A.2
  • 6
    • 33748626241 scopus 로고    scopus 로고
    • Monotonic parallel and orthogonal routing for single-layer ball grid array packages
    • Y. Tomioka and A. Takahashi, "Monotonic parallel and orthogonal routing for single-layer ball grid array packages," Proc. of ASP-DAC, pp. 642-647, 2006.
    • (2006) Proc. of ASP-DAC , pp. 642-647
    • Tomioka, Y.1    Takahashi, A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.