Wirelength reduction by using diagonal wire

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2003, Pages 104-107

  Chiang, Charles ^a   Su, Qing ^a   Chiang, Ching Shoei ^b  

^a SYNOPSYS INC   (United States)

^b NONE

Author keywords

45 routing; Diagonal routing; Routing; Steiner tree

Indexed keywords

ALGORITHMS; ROUTERS; VLSI CIRCUITS;

WIRELENGTH REDUCTION;

COMPUTER SCIENCE;

EID: 0038037500     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/764808.764836     Document Type: Conference Paper

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