DDBDD: Delay-driven BDD synthesis for FPGAs

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 910-915

  Cheng, Lei ^a   Chen, Deming ^a   Wong, Martin D F ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

Binary decision diagrams; FPGA technology mapping; Linear expansion

Indexed keywords

ALGORITHMS; BINARY DECISION DIAGRAMS; DYNAMIC PROGRAMMING; OPTIMIZATION; SYSTEMS ANALYSIS;

BDD SYNTHESIS; FPGA TECHNOLOGY MAPPING; LINEAR EXPANSION; LINEAR EXPANSION COUPLING; PERFORMANCE OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 34547348270     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1278480.1278705     Document Type: Conference Paper

References (20)

1. R. K. Brayton, G. D. Hachtel, et al. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, 1984.
2. H. Savoj, R. K. Brayton, and H. Touati. Extracting Local Dont Cares for Network Optimization. In ICCAD, pages 514-517, 1991.
3. H. Savoj and R. K. Brayton. The Use of Observability and External Dont Cares for the Simplification of Multi-Level Networks. In DAC, pages 297-301, 1991.
4. E. Sentovich, K. Singh, et al. SIS: A system for sequential circuit synthesis. Technical Report UCB/ERL Memorandum M89/49, Department of EECS, University of California, Berkeley, May 1992.
5. K. C. Chen, J. Cong, Y. Ding, A. B. Kahng, and P. Trajmar. DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. In IEEE Des. Test Comput., pages 7-20, 1992.
6. D. Chen and J. Cong. DAOmap: A Depth-optimal Area Optimization Mapping Algorithm. In ICCAD, pages 752-759, 2004.
7. J. Cong and Y. Ding. FlowMap: An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs. IEEE Trans. on CAD, 13(1):1-12, 1994.
8. A. Mishchenko, S. Chatterjee, and R. Brayton. Improvements to technology mapping for LUT-based FPGAs. In FPGA, pages 41-49, 2006.
9. C. Yang and M. Ciesielski. BDS: A BDD-Based Logic Optimization System. IEEE Trans. on CAD, 21(7):866-876, 2002.
10. N. Vemuri, P. Kalla, and R. Tessier. BDD-based Logic Synthesis for LUT-based FPGAs. IEEE Trans. on DAES, 7:501-525, 2000.
11. V. Manohararajah, D. P. Singh, and S. D. Brown. Post-Placement BDD-Based Decomposition for FPGAs. In FPL, pages 31-38, 2005.
12. R. E. Bryant. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Trans. on Computers, 35:677-691, 1986.
13. C. Y. Lee. Representation of Switching Circuits by Binary-Decision Programs. Bell System Technical Journal, 38(4):985-999, 1959.
14. S. B. Akers. Functional Testing with Binary Decision Diagrams. In Eighth Annual Conf. on FaultTolerant Computing, pages 75-82, 1978.
15. R. Rudell. Dynamic variable ordering for ordered binary decision diagrams. In ICCAD, pages 42-47, 1993.
16. C. Yang. BDD-Based Logic Synthesis System. Ph.D thesis, EECS Department, Univ. of Massachusetts, Amherst, 2000.
17. R. Rudell. Logic Synthesis for VLSI Design. Ph.D thesis, EECS Department, Univ. of California, Berkeley, 1989.
18. R. J. Francis, J. Rose, and Z. G. Vranesic. Technology Mapping Lookup Table-based FPGAs for Performance. In ICCAD, pages 568-571, 1991.
19. V. Betz, J. Rose, and A. Marquardt. Architecture and CAD for Deep-Submicron FPGAs. Kluwer Academic Publishers, 1999.
20. [Online]. Available: http://www.ecs.umass.edu/ece/tessier/rcg/bds-pga-2. 0/results_bds-pga.html.