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Volumn , Issue , 2006, Pages 5371-5374

Continuous time delta sigma modulators with reduced clock jitter sensitivity

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK JITTER SENSITIVITY; CONTINUOUS TIME DELTA SIGMA MODULATORS; NOISE ANALYSIS; PULSE-SHAPED OUTPUT SIGNALS;

EID: 34547336534     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (8)
  • 1
    • 0030401030 scopus 로고    scopus 로고
    • A 0.2 mW CMOS Δ∑ modulator for speech coding with 80 dB Dynamic Range
    • Dec
    • E. J. van der Zwan and E. C. Dijkmans, "A 0.2 mW CMOS Δ∑ modulator for speech coding with 80 dB Dynamic Range," IEEE J. Solid-State Circuits, vol. 31, pp. 1873-1880, Dec. 1996.
    • (1996) IEEE J. Solid-State Circuits , vol.31 , pp. 1873-1880
    • van der Zwan, E.J.1    Dijkmans, E.C.2
  • 2
    • 0033149028 scopus 로고    scopus 로고
    • Clock Jitter and Quantizer Metastability in Continuous-Time Delta-Sigma Modulators
    • June
    • J. A. Cherry, and W. M. Snelgrove, "Clock Jitter and Quantizer Metastability in Continuous-Time Delta-Sigma Modulators," IEEE Trans. on Circuit and System II., Vol. 46. No. 6, June 1999.
    • (1999) IEEE Trans. on Circuit and System II , vol.46 , Issue.6
    • Cherry, J.A.1    Snelgrove, W.M.2
  • 3
    • 34547246012 scopus 로고    scopus 로고
    • Younis Saed O, Butterfield D. K, Method and apparatus for eliminating clock-jitter in continuous-time delta-sigma analog-to-digital converter Australian Patent 0 036 750, June 22, 2000
    • Younis Saed O, Butterfield D. K., "Method and apparatus for eliminating clock-jitter in continuous-time delta-sigma analog-to-digital converter" Australian Patent 0 036 750, June 22, 2000.
  • 4
    • 0346342400 scopus 로고    scopus 로고
    • A triple-mode continuous-time sigma-delta modulator with switched-capacitor feedback DAC for GSM-EDGE/CDMA2000/UMTS Receivers
    • December
    • R. h.M. Van Veldhoven, "A triple-mode continuous-time sigma-delta modulator with switched-capacitor feedback DAC for GSM-EDGE/CDMA2000/UMTS Receivers IEEE J. Solid-State Circuits, Vol. 38, No. 12, December 2003.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.12
    • Van Veldhoven, R.H.M.1
  • 5
    • 84893789916 scopus 로고    scopus 로고
    • A continuous-time sigma-delta modulator with reduced, jitter sensitivity
    • M. Ortmanns, et. al. "A continuous-time sigma-delta modulator with reduced, jitter sensitivity," ESSCIRC, 2002.
    • (2002) ESSCIRC
    • Ortmanns, M.1    et., al.2
  • 6
    • 34748855834 scopus 로고    scopus 로고
    • Technique and method for Suppressing Clock-Jitter in Continuous-Time Delta-Sigma Modulators,
    • International Patent App, PCT/GB 2005/004832
    • H. Zare-Hpseini, I. Kale, C. S. Morling "Technique and method for Suppressing Clock-Jitter in Continuous-Time Delta-Sigma Modulators," International Patent App., PCT/GB 2005/004832.
    • Zare-Hpseini, H.1    Kale, I.2    Morling, C.S.3
  • 7
    • 80053287950 scopus 로고    scopus 로고
    • High Performance Delta-Sigma ADC Using A Feedback NRZ SIN signal
    • US patent, NO. 0140590 A1, Oct. 2002
    • A. Eshraghi et. al.," High Performance Delta-Sigma ADC Using A Feedback NRZ SIN signal." US patent, NO. 0140590 A1, Oct. 2002.
    • Eshraghi, A.1    et., al.2
  • 8
    • 34547320108 scopus 로고    scopus 로고
    • Technique and method for Suppressing Clock-Jitter in Continuous-Time Delta-Sigma Modulators
    • Nov
    • S. Luschas, and H. S. Lee, "Technique and method for Suppressing Clock-Jitter in Continuous-Time Delta-Sigma Modulators," IEEE Trans. on Circuit and System II., Vol. 49, No. 11, Nov. 2002.
    • (2002) IEEE Trans. on Circuit and System II , vol.49 , Issue.11
    • Luschas, S.1    Lee, H.S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.