A new bulk-driven input stage design for sub 1-volt CMOS op-amps

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 1547-1550

  Haga, Yasutaka ^a   Morling, Richard C S ^a   Kale, Izzet ^a,b  

^a UNIVERSITY OF WESTMINSTER   (United Kingdom)

^b EASTERN MEDITERRANEAN UNIVERSITY   (Turkey)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; TRANSCONDUCTANCE;

CMOS TECHNOLOGY; SLEW RATE; SUPPLY VOLTAGE; WIDE SUPPLY VOLTAGE;

OPERATIONAL AMPLIFIERS;

EID: 34547314458     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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