Body-driving as a low-voltage analog design technique for CMOS technology

2000 Southwest Symposium on Mixed-Signal Design, SSMSD 2000

Volumn , Issue , 2000, Pages 113-118

  Blalock, B J ^a   Li, H W ^b   Allen, P E ^c   Jackson, S A ^a  

^a MISSISSIPPI STATE UNIVERSITY   (United States)

^b UNIVERSITY OF IDAHO   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; INTEGRATED CIRCUIT DESIGN; MIXED SIGNAL INTEGRATED CIRCUITS; POWER AMPLIFIERS; TOPOLOGY;

ANALOG DESIGN; BODY DRIVING; CLASS-AB; CMOS TECHNOLOGY; FOUR-QUADRANT MULTIPLIER; LOW VOLTAGES; OUTPUT STAGES;

SILICON ON INSULATOR TECHNOLOGY;

EID: 84962030343     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SSMSD.2000.836457     Document Type: Conference Paper

References (19)

1. J.D. Meindl, "Low Power Microelectronics: Retrospect and Prospect," Proceedings of the IEEE, pp. 619-635, April 1995.
2. A.P. Chandrakasa, S. Sheng, and R.W, Brodersen, "Low-Power CMOS Digital Design," IEEE J. of Solid State Circuits, pp. 473-484, April 1992.
3. S. Cristoloveanu, "Silicon on Insulator Technology," The VLSI Handbook, CRC Press/IEEE Press, Boca Raton, FL, 2000.
4. J-P. Eggermont, D. DeCeuster, D. Flandre, B. Gentinne, P. G. Jespers, and J-P Colinge, "Design of SOI CMOS Operational Amplifiers for Applications up to 300 K," IEEE J. of Solid State Circuits, pp. 179-186, Feb. 1996.
5. S. Kuge, F. Morishita, T. Tsuruda, S. Tomishima, M. Tsukude, T. Yamagata and K. Arimoto, "SOI-DRAM Circuit Technologies for Low Power High Speed Multigiga Scale Memories," IEEE J. of Solid State Circuits, pp. 586-591, April 1996.
6. Y-H. Koh, et al., "One Gigabit SOI DRAM with Fully Bulk Compatible Process and Body-Contacted SOI MOSFET Structure," IEDM Technical Digest, pp. 579, 1997.
7. B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, "Designing 1-V Op Amps using Standard Digital CMOS Technology," IEEE Trans. on Circuits and Systems II, vol. 45, no. 7, pp. 769-780, July 1998.
8. E. A. Vittoz, "MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology," IEEE J. Solid-State Circuits, vol. vol. SC-18, pp. 273-279, June 1983.
9. T. Pan and A. A. Abidi, "A 50-dB Variable Gain Amplifier Using Parasitic Bipolar Transistors in CMOS," IEEE J. Solid-State Circuits, vol. SC-24, pp. 951-961, Aug. 1989.
10. B. J. Blalock, "A 1-Volt CMOS Wide Dynamic Range Operational Amplifier," (Ph.D. Dissertation, School of ECE, Georgia Institute of Technology, Atlanta, GA, 1996).
11. P. T. Skelly, and The Boeing Company, Solid State Electronics Development.
12. B. J. Blalock and S. A. Jackson, "A 1.2-V CMOS Four-Quadrant Analog Multiplier," Proc. 1999 Southwest Symp. on Mixed-Signal Design, 1999, pp. 1-4.
13. R. Sarpeshkar, R. F. Lyon, C. A. Mead, "An Analog VLSI Cochlea with New Transconductance Amplifiers and Nonlinear Gain Control," Proc. ISCAS, 1996, vol. 3, pp. 292-296.
14. A. Guzinski, M. Bialko, and J. C. Matheau, "Body Driven Differential Amplifier for Application in Continuous-Time Active C-Filter," Proc. ECCD, Paris, France, 1987, pp. 315-319.
15. B. J. Blalock and P. E. Allen, "A One-Volt, 120-μW, 1-MHz OTA for Standard CMOS technology," Proc. ISCAS, 1996, vol. 1, pp. 305-307.
16. P. E. Allen, B. J. Blalock, and G. A. Rincon, "A 1V CMOS Op amp Using Bulk-Driven MOSFETs," Dig. ISSCC '95, Feb. 1995, San Francisco, CA, pp. 192-193.
17. J. P. Uyemura, Circuit Design for CMOS VLSI. Boston: Kluwer Academic Publishers, 1992.
18. J. P. Colinge et al., "Potential of SOI for Analog and Mixed Analog-Digital Low-Power Applications," Dig. ISSCC '95, Feb. 1995, San Francisco, CA, pp. 194-195.
19. J. F. Duque-Carrillo, R. Perez-Aloe, and J. M. Valverde, "Biasing circuit for high input swing operational amplifiers," IEEE J. Solid-State Circuits, vol. SC-30, pp. 156-159, Feb. 1995.