The effect of clock jitter on the DR of ∑Δ modulators

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 2009-2012

  Van Veldhoven, Robert ^a   Nuijten, Peter ^a   Van Zeijl, Paul ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

FEEDBACK; JITTER; PHASE NOISE; TOPOLOGY;

DAC TOPOLOGIES; DYNAMIC RANGE (DR); SPURIOUS TONES;

MODULATORS;

EID: 34547295778     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. P. Nuijten, "The effects of phase lock loop jitter on the performance of A/D and D/A converters", Philips internal report, 1993
2. R.H.M. van Veldhoven, "A triple-mode continuous-time Sigma-Delta modulator with switched-eapacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver", IEEE JSSC, vol. 38, pp.2069-2076, Dec. 2003
3. K.Philips, "A 4.4mW 76dB complex Sigma-Delta ADC for Bluetooth receivers", IEEE ISSCC 2003 Digest, vol..1, pp.64-478
4. L. Brecms, "A cascaded continuous-time Sigma-Delta Modulator with 67-dB dynamic range in 10-MHz bandwidth", IEEE JSSC, Vol. 39, Dec. 2004, pp. 2152-2160
5. P. van Zeijl, R.H.M. van Veldhoven, P. Nuijten, "Sigma-Delta ADC Clock jitter in (Low) IF receiver architectures", subm. to ISCAS 2006