High-speed CRC design for 10 Gbps applications

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2006, Pages 3177-3180

  Lin, Jing Shiun ^a   Lee, Chung Kung ^a   Shieh, Ming Der ^a   Chen, Jun Hong ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; LINEAR SYSTEMS; SHIFT REGISTERS; STATE SPACE METHODS;

COMPANION METRIC; CYCLIC REDUNDANCY CODES (CRCS); OUTPUT BLOCK;

INTEGRATED CIRCUIT LAYOUT;

EID: 34547285800     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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3. A. M. Patel, "A multi-channel CRC register", in AFIPS Conference Proceedings, vol. 38, pp. 11-14, Spring 1971.
4. G. Albertengo and R. Sisto, "Parallel CRC generation", IEEE Micro, vol. 10, pp. 63-71, Oct. 1990.
5. T-B. Pei and C. Zukowski, "High-speed parallel CRC circuits in VLSI",IEEE Trans. Commun., vol. 40, pp. 653-657, April 1992.
6. R. J. Glaise, "A two-step computation of cyclic redundancy code CRC-32 for ATM networks", IBM J. Res. Devel., vol. 41, pp. 705-709, Nov. 1997
7. J.H. Derby, "High-speed CRC computation using state-space transformations," in Proc. Global Telecommunicaton Conference, Vol. 1, pp. 166-170, Nov. 2001.
8. M. D. Shieh, H. F. Lo, and M. H. Sheu, "A systematic approach for parallel CRC Computation," Journal Information Science and Engineering Vol. 17, pp. 445-461, May 2001.