A low current consumption CMOS latched comparator for body-implanted chip

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1940-1943

  Kiyoyama, K ^a   Onoda, M ^b   Tanaka, Y ^a  

^a NAGASAKI INSTITUTE OF APPLIED SCIENCE   (Japan)

^b TERUMO CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT CONSUMPTION; DELTA-SIGMA; GATE-SOURCE VOLTAGE; LOW CURRENTS; POST LAYOUT SIMULATION; POWER SUPPLY; STANDARD CMOS TECHNOLOGY; SUBTHRESHOLD;

CMOS INTEGRATED CIRCUITS; MEDICAL APPLICATIONS;

COMPARATORS (OPTICAL);

EID: 34547240096     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464993     Document Type: Conference Paper

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