An automated, reconfigurable, low-power RFID tag

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 131-136

  Jones, Alex K ^a   Hoare, Raymond R ^a   Dontharaju, Swapna R ^a   Tung, Shenchih ^a   Sprang, Ralph ^a   Fazekas, Josh ^a   Cain, James T ^a   Mickle, Marlin H ^a  

^a PA 15260   (United States)

Author keywords

Design; Human factors; Languages; Performance

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BUFFER STORAGE; COMPUTER HARDWARE; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PROGRAM PROCESSORS; TRANSCEIVERS;

ANSI-C; CPLD; EISC PROCESSORS; RFID TAG;

ELECTRONIC DOCUMENT IDENTIFICATION SYSTEMS;

EID: 34547141888     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146948     Document Type: Conference Paper

References (21)

1. P. Blythe. RFID for road tolling, road-use pricing and vehicle access control. IEE Colloquium on RFID Technology, 1999.
2. A. Cerino and W. P. Walsh. Research and application of radio frequency identification (RFID) technology to enhance aviation security. In Proc. IEEE NAECON, 2000.
3. Y. Cha. EISC core. ADChips Presentation, February 2005.
4. I. Chlamtac, C. Petrioli, and J. Redi. Energy-conserving access protocols for identification networks. IEEE/ACM Transactions on Networking (TON), 7(1), February 1999.
5. C. Gilberto, M. Martonosi, J. Peng, R. Ju, and G. Lueh. XTREM: A power simulator for the Intel XScale core. In Proc. ACM LCTES, 2004.
6. R. Hoare, A. K. Jones, D. Kusic, J. Fazekas, J. Foster, S. Tung, and M. McCloud. Rapid VLIW processor customization for signal processing applications using combinational hardware functions. EURASIP Journal on Applied Signal Processing, 2006.
7. Intel. SA-110 microprocessor technical reference manual, 1998. ftp://download.intel.com.
8. Intel. Intel PXA27x processor family developers manual, 2004. ftp://download.intel.com.
9. A. K. Jones, R. Hoare, S. R. Dontharaju, S. Tung, , R. Sprang, J. Fazekas, J. T. Cain, and M. H. Mickle. An automated, FPGA-based reconfigurable, low-power RFID tag. Journal of Microprocessors and Microsystems, to appear.
10. A. K. Jones, R. Hoare, D. Kusic, J. Fazekas, and J. Foster. An FPGA-based VLIW processor with custom hardware execution. In Proc. of FPGA, 2005.
11. A. K. Jones, R. Hoare, D. Kusic, G. Mehta, J. Fazekas, and J. Foster. Reducing power while increasing performance with supercisc. ACM TECS, to appear.
12. M. Kaundinya and A. Syed. Modeling event driven applications with a specification language (MEDASL). In Proc. ACM OOPSLA, 2004.
13. C. Li, L. Liu, S. Chen, C. C. Wu, C. Huang, and X. Chen. Mobile healthcare service system using RFID. In Proc. IEEE ICNSC, volume 2, 2004.
14. L. M. Ni, Y. Liu, Y. C. Lau, and A. P. Paul LANDMARC: indoor location sensing using active RFID. Wireless Networks, 10, November 2004.
15. J. Russell and M. Jacome. Software power estimation and optimization for high performance, 32-bit embedded processors. In Proc. of ICCD, 1998.
16. D. Shuping and W. Wright. Geotime visualization of RFID supply chain data. RFID Journal, March 2005.
17. Sim-panalyzer. Simplescalar-ARM power modeling project. http://www.eecs.umich.edu/panalyzer.
18. T. Bray and J. Paoli and C. M. Sperberg-McQueen. Extensible markup language (XML) 1.0. W3C Recommendation, 1998. http://www.w3.org/TR/1998/REC-xml- 19980210.
19. X. Tang, T. Jiang, A. Jones, and P. Banerjee. Compiler optimizations in the PACT behavioral synthesis tool for ASICs and FPGAs. In Proc. of SoC, September 2003.
20. TI. Texas instruments' RFID technology streamlines management of Vatican library's treasured collections, 2004.
21. F. Zhou, C. Chen, D. Jin, C. Huang, and H. Min. Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. In Proc. ISLPED, 2004.